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Making Cache Coherent SoC Design Easier with Ncore™ IP from Arteris

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"Making Cache Coherent SoC Design Easier with Ncore™ IP from Arteris"

Addressing System-on-chip complexity and future trends

As the number and variety of computing elements in SoCs grow, specific application areas require a tight connection of processing elements through coherency. Interconnect IP makes cache coherent SoC designs easier, saving 50+ person-years effort per project vs DIY solutions.

Explore the challenges in designing cache coherent SoC architectures. Understand the role cache coherency plays in maintaining data integrity across different cache levels. Learn about interconnect IP as a solution 

The following themes are explored:

  • Growing SoC design challenges amid the complexity of multi-core processors, diverse processing elements, and on-chip communication.
  • Insights into all types of cache coherency and non-coherency and their relevance in optimizing performance across diverse processing elements.
  • A solution called Ncore Interconnect IP for cache coherent SoC designs offering true heterogeneous cache coherency, scalability, ISO 26262 certification.

Offered Free by: Arteris
See All Resources from: Arteris

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